The News: RISC-V International unveiled its first four Instruction Set Architecture (ISA) specifications and extensions for 2022, bringing new capabilities to RISC-V-based chip designs and the open design RISC-V community. The new specifications and extensions for 2022 follow 16 specifications representing 40 extensions that were unveiled in 2021, further broadening the open chip design specs for a wide range of industries. Read the full RISC-V Press Release.
RISC-V International Adds Four ISA Chip Specification Approvals
Analyst Take: RISC-V International’s latest expansion of its RISC-V ISA specifications and extensions for chip makers is big news, providing chip designers and chip makers with even more custom tools to create the right chips for needed tasks from IoT to vehicles to industry, computers and more.
In this latest round of approved ISA specifications and extensions, RISC-V International has approved IS specifications for Efficient Trace for RISC-V (E-Trace), RISC-V Supervisor Binary Interface (SBI), RISC-V Unified Extensible Firmware Interface (UEFI) specifications, and the RISC-V Zmmul multiply-only extension.
According to the non-profit home of the open standard RISC-V ISA platform, this is just the start of new ISA specifications and extensions for RISC-V in 2022. The group stated that at least six more specifications are also in the pipeline this year for components that will extend into vertical applications.
The new tools add critical tools for RISC-V chip developers, including E-Trace for RISC-V, a debugging tool which provides a standard way to do processor trace efficiently for embedded system design, up to large, powerful computers. These are the kinds of evolutionary improvements and refinements that make RISC-V such a trusted organization for chip makers to work with in their designs. As chip designs get smaller and more complex, I believe the importance and trust in those relationships cannot be overstated.
The new RISC-V SBI specification will allow chip developers to port supervisor-mode software across all RISC-V implementations, allowing developers to write something once and apply it everywhere. These kinds of flexible code-writing tools are essential today, adding immense capabilities for chip designers on the fly.
To provide these capabilities, RISC-V specification for SBI architects a firmware layer between the hardware platform and the operating system kernel using an application binary interface in supervisor mode (S-mode or VS-mode). Many members of RISC-V International already implemented the RISC-V SBI specification in their RISC-V products, so the recent ratification of the specification by the group ensures a standard approach across the entire RISC-V ecosystem, ensuring compatibility. Again, this is huge for chip designers who can rely on built-in compatibility and standards, which improves their designs.
Also recently approved are new RISC-V UEFI Protocols, which will allow chip developers to bring existing UEFI standards onto RISC-V platforms, and the RISC-V Zmmul Multiply Only extension, which enables low-cost implementations that require multiplication operations but not division.
Why the New RISC-V Specifications are Important
With standardization and increased compatibility for RISC-V International’s specifications, chip designers and product makers gain tools that enable better silicon designs and chips. In every industry, this is a boon for productivity, quality and performance.
This will be an interesting segment to watch long into the future as RISC-V International continues to bolster its specifications and extensions for chip designers to incorporate into their latest ideas. Better specifications and code produce better results, and that mantra is central to the work of RISC-V International. RISC-V’s modular technical approach and its open, royalty-free license model provide massive resources for chip designers while lowering the costs of innovation. That is an important combination for every industry.
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Analysis and opinions expressed herein are specific to the analyst individually and data and other information that might have been provided for validation, not those of Futurum Research as a whole.
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